FIG. 1 illustrates a simplified circuit diagram of an example of a smart power switching module 100 for use within, for example, an alternator regulator. The smart power switching module 100 comprises a power switching device (Field Effect Transistor—FET) 110 operably coupled between a battery/alternator supply 102 and an output 104 of the power switching module 100. The power switching device 110 is controllable via a gate signal 114 to allow a load current (I_LOAD) 112 to flow there through, from the battery/alternator supply 102 to the output 104 of the power switching module 100.
The power switching module 100 further comprises a current sense component for the load current (I_LOAD) 112. The current sense component comprises a differential or error amplifier 130 comprising a first (inverting) input operably coupled to a source node 115 of the power switching device 110. In this manner, the first (inverse) input of the differential amplifier 130 is arranged to receive a voltage signal representative of the voltage level of the battery/alternator supply 102 less the potential difference across the power switching device 110.
The differential amplifier 130 further comprises a second (non-inverting) input arranged to receive a current sense feedback signal generated by a current sense feedback component of the current sense component. The current sense feedback component comprises a sense switching device (FET) 120 operably coupled between the battery/alternator supply 102 and a ground plane 106. The sense switching device 120 is controllable by the same gate signal 114 as the power switching device 110. In this manner, the current flow through the sense switching device 120 is representative of the current flow through the power switching device 110. A source node 125 of the sense switching device 120 is operably coupled to the second (non-inverting) input of the differential amplifier 130. In this manner, the second (non-inverting) input of the differential amplifier 130 is arranged to receive a voltage signal representative of the voltage level of the battery/alternator supply 102 less the potential difference across the sense switching device 120.
A feedback transistor 140 is operably coupled between the source node 125 of the sense switching device 120 and the ground plane 106. A gate of the feedback transistor 140 is operably coupled to a (positive) output of the differential amplifier 130. In this manner, the sense switching device 120 and the feedback transistor 140 are operably coupled in series, with the sense switching device 120 being controllable via the gate signal 114 and the feedback transistor 140 being controllable via the output of the differential amplifier 130. The differential amplifier 130 is arranged to control the current I_SENSE 122 through the feedback transistor 140 such that substantially equal voltage potentials are maintained at its inputs, and thus at the source nodes 115, 125 of the power switching device 110 and sense switching device 120.
Significantly, by maintaining substantially equal voltage potentials at the source nodes 115, 125 of the power switching device 110 and sense switching device 120, and because the sense switching device 120 is controlled by the same gate signal 114 as the power switching device 110, the current I_SENSE 122 is proportional to the load current (I_LOAD) 112. The feedback transistor 140 effectively acts as a voltage to current converter, converting the voltage signal output by the differential amplifier 130 into the current I_SENSE 122. As such, the voltage signal output by the differential amplifier 130 may be considered as being representative of the load current (I_LOAD) 112.
The output of the error amplifier 130 is further provided to a gate of a voltage-to-current converter transistor 150, which converts the output signal of the error amplifier 130 into a sense current I_SNS 160 representative of the current I_SENSE 122. The sense current I_SNS 160 is sourced from an input of an analogue to digital converter (ADC) 170. The ADC 170 also receives a reference current 165 and outputs a digital code 175 based on an integer representative of the ratio of the sense current I_SNS 160 and the reference current 165.
The current recopy ratio between the power switching device 110 and the sense switching device 120 is primarily dependent on the ratio of the geometries of the two devices. However, parasitic metal on-resistance of the routing for the source and drain nodes of the power switching device 110 can be another significant contributing factor to the recopy ratio between the power switching device 110 and the sense switching device 120. Specifically, parasitic metal on-resistance of the routing for the source and drain nodes of the power switching device 110 affects the absolute value of the recopy ratio and also creates a significant temperature coefficient for the recopy ratio.
The next generation of alternator regulators are required to provide a digital code for the value of the load current with a 2% accuracy across all conditions. Consequently, all contributors to inaccuracy have to individually achieve an error budget much less than 2%. The current recopy ratio between the power switching device 110 and the sense switching device 120 is one such contributor. The absolute value of the recopy ratio may be trimmed out at room temperature.
However, the temperature coefficient of the recopy ratio cannot be trimmed out, and thus can be problematic when trying to achieve the <2% accuracy at temperatures other than room temperature, and in particular at extreme temperatures. The recopy ratio between a large geometry, e.g. of the order of 1 mm2, power switching device 110 and a sense switching device 120 may have a temperature coefficient drift in the order of +/−10-15% for a temperature range from −40 deg C. to +150 deg C. For example, for a Smart MOS 8MV 45V NLD Power MOS with channel width of 750 um and 294 parallel gates, the main FET (i.e. power switching device 110) comprises a geometry of 1.25×0.78 mm. The sense FET (i.e. sense switching device 120) geometries may be chosen to achieve a recopy ratio of 1:147. However when parasitic source and drain routing resistance of the Main FET are taken into account, the actual recopy ratio may be in the range of 1:77 to 1:87 for a temperature range from −40 deg C. to +150 deg C., which represents +/−12% temperature drift.
Monolithic power switches with current reporting functionality face a similar challenge in relation to sensing the load current with a 2% accuracy across all conditions. Any product that requires accurate sensing of the current through a power switching device for diagnostic or reporting purposes may face the same challenge of compensating for the temperature coefficient of the recopy ratio.